Embodiments of the inventive concept described herein relate to a junctionless transistor and a method of manufacturing the same, and more particularly, relate to a junctionless transistor based on vertically integrated gate-all-round multiple nanowire and a method of manufacturing the same.
A Moore's law is discovered in a semiconductor transistor, and through continuous scaling down, the semiconductor transistor has undergone lots of innovative evolution of scaling down technology which happened about 20 times over last 45 years. As a result, a gate length of a metal-oxide-semiconductor field-effect-transistor (MOSFET) is decreased by 70% every 2.5 years on average, and therefore the gate length decreased by one-four hundredth of an initial gate length over last 45 years.
Scaling down has continuously proceeded, a silicon technology begun to mass-produce transistors each of which had a gate length of less than 100 nm since 2000, and this meant that a nanoscale electronic device has begun. However, after this time, scale down has reached a plateau from time to time such that not only physical limitation of a manufacturing process was exposed, but also side effects were caused in terms of performance. A short channel effect (SCE) due to decrease of the gate length is a representative side effect. Although the extreme gate length of sub-10 nm is not reached, increase of off-state leakage current derived from the short channel effect prevents present and future MOSFET scale down.
A gate-all-around nanowire channel structure is evaluated as the most effective structure for preventing increase of leakage current derived from the short channel effect.
Hereupon, below embodiments provide a vertically integrated gate-all-around multiple nanowire field-effect transistor.
Most existing semiconductor transistors today are based on a junction. The junction allows flow and blocking of mobile charges to be easy, thereby functioning to strengthen a function of the semiconductor transistor. Accordingly, the junction has been considered as an essential component of a transistor. A junctionless transistor which has broken stereotypes of a conventional transistor has received a lot of attention from academic circles and industrial circles as a next-generation transistor, with development thereof, due to a simple manufacturing process and various advantages of operation.
However, absence of the junction requires superior gate controlling ability than the conventional junction-based transistor in terms of stable on-off switching. Namely, on-off switching depends on only the gate controlling ability without junction support. Meanwhile, development of a high-performance junctionless transistor has mainly focused on decrease of resistance of a channel which is a passage for electrons. To this end, a high-concentration channel ion implantation process has been applied. However, a scattering effect due to increased doping dopants causes performance degradation, thereby requiring a proper compromise with channel resistance. Basically, the best method for high-performance of the transistor is to increase a length of a channel region—there are no two ways about it. However, considering scalability and integration for continuous scale down and a gate controlling ability of the channel, the above method is not suitable. Accordingly, development of the junctionless transistor for the next generation electronics industry acutely requires excellent gate controlling ability, high performance, and optimization of superior scalability.
A vertically integrated gate-all-around multiple nanowire field-effect transistor is an optimum structure to satisfy excellent gate controlling ability, high performance, and high scalability. However, a conventional vertically integrated gate-all-around multiple nanowire field-effect transistor reduces completeness of the transistor due to complexity of a process in which a plurality of nanowires is vertically integrated and variability.
In detail, in the conventional vertically integrated gate-all-around multiple nanowire field-effect transistor, there are many problems, e.g. performance variability due to each shape and size ununiformity of the nanowires, difficulty of formation of the multiple nanowires which have uniform doping concentration using a source-drain ion implantation process and an annealing process, resistance ununiformity of source and drain electrodes and channel caused by the above problem, and sensitivity of transistor performance against a corner effect of the nanowire channel.
Accordingly, following embodiments provide a junctionless transistor based on a vertically integrated gate-all-around multiple nanowire channel which solves the problems of the conventional vertically integrated gate-all-around multiple nanowire field-effect transistor, and a method of manufacturing the same.